While many types of integrated circuits may be designed to operate with a single internal voltage, it is often desirable to provide an integrated circuit (IC) including devices (e.g., transistors as well as passive circuit elements) that operate at two or more different voltage levels. Examples of such ICs include a Non-Volatile Memories (NVM) and ICs including a NVM or a flash macro or memory, such as a micro-controller, microprocessor or programmable system on a chip (PSOC). Such a circuit typically includes low-voltage metal-oxide-semiconductor (LV_MOS) transistors used in logic and/or switching applications and designed to operate at a voltage of less than from about 2.5 to about 3.3 volts (V), and other high-voltage metal-oxide-semiconductor (HV_MOS) transistors used in NVM applications such as charge pumps, HV switches, sector selectors, input/output (I/O) cells or drivers, and typically designed to operate at voltages of about 9V or greater.
One approach to integrating a HV_MOS transistor into such a circuit includes introducing drain-extended (DE) architectures to provide transistors having higher breakdown voltages (BV) for use in high power and high voltage applications. Briefly, in a DE transistor the drain is extended by implanting low doped semiconductor region which depletes during reverse biasing, thereby allowing much of voltage to be dropped across a drain extension in the substrate, and thereby reducing the electric field across a gate oxide to a safe level. In existing complementary metal-oxide-semiconductor (CMOS) process flows the DE implants are done using masks and implants borrowed from other devices in baseline process. However, as the size of the transistors advance to less than 65 nanometers (nm) many of these masks and implants are not used. Instead, only well masks are used (including both deep and shallow implants) and halo/tip implants are used control a threshold voltage (VT) of the transistor.
Thus, there is a need for a method of forming DEMOS transistors with a high BV that is compatible with process flows fabricating transistors at 65 nm and beyond. It is further desirable that the method substantially does not introduce any new mask and/or implant steps to the process flow.